Semiconductor circuit fabrication is evolving to meet ever increasing demands for higher switching speeds and lower power consumption. For applications requiring large computational power, there is a need for higher device switching speeds at a given power level. For mobile applications, there is a need for lower power consumption levels at a given switching speed. Increased device switching speeds are attained by reducing the junction capacitance. Reduced power consumption is attained by reducing parasitic leakage current from each device to the substrate. Both reduced junction capacitance and reduced parasitic leakage current is attained by forming devices on multiple silicon islands formed on an insulating (silicon dioxide) layer on the semiconductor substrate, each island being electrically insulated from all other islands by the silicon dioxide layer. Such a structure is called a silicon-on-insulator (SOI) structure.
SOI structures may be formed in a layer transfer process in which a crystalline silicon wafer is bonded to the top of a silicon dioxide layer previously formed on another crystalline silicon wafer. Van der Wals forces cause the two wafers to adhere immediately, allowing a stronger bond to be formed thereafter by heating the conjoined wafers in an anneal step. The “top” wafer forming the active semiconductor layer is then cleaved along a plane and the upper portion removed to provide a suitably thin active semiconductor layer thickness.
While such SOI structures provide the desired increase in device speed and/or decrease in power consumption, they are susceptible to failure by separation at the interface where the two wafers are conjoined. This is because the silicon-to-silicon dioxide atomic bonds between the two wafers are or can be imperfect, in that they are not identical to (not as dense as) the ideal silicon-to-silicon dioxide bonds between a silicon wafer and the silicon dioxide layer formed on that wafer by a thermal process. The chief reason for this is that the proportion of atomic sites at each wafer surface available for bonding between the two wafers is less than in the case of the ideal example of a thermal oxide layer formed on a silicon substrate.
The problem of the tendency of SOI structures to failure by separation has thus far rendered SOI structures less useful than had been anticipated, so that the need for higher device speed and lower power consumption has not been fully met.
Another cause of the cleavage or separation problem is the susceptibility of the wafer-to-wafer bond to failure in the presence of contamination on the surface of either wafer prior to wafer-to-wafer bonding. Thus, the SOI fabrication process is highly sensitive to contamination and is relatively unreliable as a result.
Another problem that must be addressed in SOI fabrication is the amending of the cleaved surface of the top active silicon layer to form a high quality smooth crystalline surface that is at least nearly as good as the surface of a crystalline silicon wafer. This is important because charge mobility of devices formed in the active layer depend upon the crystalline quality of the surface of the active layer. Currently, this need is addressed by chemical mechanical polishing of the cleaved surface of the active layer. The problem is that chemical mechanical polishing can leave imperfections in the surface and must be carried out in a separate apparatus, is relatively slow, and therefore represents a significant cost factor in the SOI fabrication process.
A further problem of the SOI fabrication process is that the cleavage of the “top” silicon layer along a true plane to form a thin active layer requires implantation of ions along an entire plane defining the cleavage plane at some predetermined uniform depth below the surface. With conventional ion implantation techniques, a thin ion beam must be rastered across the entire area of the wafer until the entire cleavage plane has received a uniform predetermined ion dose (number of ions per unit area of the cleavage plane). This is a problem because the ion implantation step requires an inordinate amount of time (on the order of hours for a 300 mm wafer, for example), and therefore represents a further significant cost factor. As a result of this and other factors, SOI fabrication costs are so excessive relative to conventional semiconductor circuit structures, that they are not competitive except where the need for high speed or low power consumption is overwhelming. As a result, SOI structures currently find very limited use.
What is needed, therefore, is a solution to the problem of an inherently weak or non-ideal bond between the conjoined wafers, the pronounced susceptibility of the SOI process to contamination, the required use of a chemical mechanical polishing step in the SOI fabrication process, and the costly ion implantation step for forming the cleavage plane of the active layer.